EM-415

HDL Synthesis

This course introduces the student to VHDL (VHSIC (Very High Speed Integrated Circuit) Hardware Description Language) and applications with a Field-Programmable Gate Array (FPGA). Students will focus on design synthesis to implement basic combinational and sequential logic operations including more advanced topics such as signal decoding and state machine applications. FPGA functional and post-route timing simulation is studied to verify timing and assist during development. Asynchronous external interfacing topics are discussed and implemented to provide students with solutions to many common challenges in FPGA design.

Credit Hours

42

Min. Grade

0%